【T112017-数据工程和技术分会场】物联网和人工智能领域内置芯片分析的意外之旅.pdf

Future-proofing BI: an unexpected journey to leverage‘In-Chip’ analytics in IoT and AIAni ManianHead of Product Strategy| Talking dataSIMPLIFYING Business Analytics for COMPLEX Data“The key strength of Sisense is the platform’s capability to easily handle and manage large and diverse datasets, and analyze them in dashboards based on its proprietary In-Chip technology.”- Gartner Magic Quadrant| Talking dataHOW IT ALL STARTED| Talking dataWHAT DO FIVE DATA GEEK STUDENTS DREAM ABOUT?| Talking dataWELL, BELIEVING THEY’RE BADASS… THEY’RE DREAMING OF…| Talking dataBEER & CHIPS| Talking dataBeerDataIN ORDER TO UNDERSTAND IN-CHIPANALYTICSLET’S ASSUME THAT:| Talking dataMEMORY HIERARCHY IN MODERN CPUSL3 CacheCapacity:6MB-20MBLatency:35 CyclesL2 CacheCapacity:256KB-1MBLatency:10 CyclesL1 CacheCapacity:64KB-128KBLatency:3 CyclesCPUMain MemoryCapacity:GBs-TBsLatency:150-450 CyclesRAMRAMRAMDiskCapacity:UnlimitedLatency:1M CyclesDISK| Talking dataSO, WHY SHOULD WE EVEN CARE?Slowdown when fetching new data to the CPUx50SlowdownMain MemoryUp tox100x10SlowdownL3 Cachex3SlowdownL2 Cache| Talking dataMEMORY BANDWIDTH L1 cacheHome fridge DistanceImmediateCustomerx1L2 / l3 cacheShopDistanceBicycleCustomerx10RamSupermarketDistanceCar Customerx50DiskBreweryDistanceAirplaneCustomerIf data equals beer then data storage units equal all the places beer is kept!| Talking dataTHERE SHOULD HAVE BEEN A SLIDE HERE..(it’s the beer’s fault…)How does Sisense overcome the memory bottleneck?| Talking dataStore all data on the DiskOnly Use RAM When a Query RunsLoad Only the Relevant Columns in RAMHOW DOES SISENSE OVERCOME THE MEMORY BOTTLENECK?VECTORIZATIONJIT LLVM & SIMD| Talking dataVECTORIZATION & CACHE AWARENESSL1 CacheFirst into RAMOP1004K(Values)1004K(Values)1004K(Values)Result VectorPush Back To RAM1004K(Values)SIMD REGISTERApply Operation On 4/8 Data Elements SimultaneouslyOPOPColumn 41004K(Values)ResultVector1004K(Values)Column 11004K(Values)Column 21004K(Values)Column 31004K(Values)| Talking dataJIT LLVM COMPILATION WITH SIMD SUPPORTint f {int a, int b){elsem0m1m2m3~m0m1m2m3Return a; a0a1a2a3returna= 0;a0a1a2a30000withmaskm0m1m2m3if {a <0)m0m1m2m3a0a1a2a3<0000a+ =b;a0a1a2a3b0b1b2b3withmaskm0m1m2m3“SIMD” (Single Instruction, Multiple Data) is the process of rewriting a loop so that instead of processing a single element of an array N times, it processes (say) 4 elements of the array simultaneously N/4 times.| Talking dataf1 Vector“Beer 1”“Beer 2”Mask VectorORf4 Vector>10=0/=1OR&Mask Vectorf2 Vector“Customer 1”“Customer 2”OR&Mask Vectorf3 Vector“1”/”2”/”3”OR&Mask VectorL1 CacheField Vector = ValueMask Vector = True / FalseSELECT(f1 = “beer1” OR f1 = “beer2”) ANDFROM T1 (f2 = “customer1” OR f2 = “customer2”) ANDWHERE(f3 = “1” OR f3 = “2” OR f3 = “3”) AND(f4>”10” OR f4 = “0” OR f4 = “1”)| Talking dataNEXT: PERFORMANCE TUNING FOR MANY USERSADD INSTANCESADD HARDWAREOPTIMIZE DATA MODELHOW CAN YOU DELAY USING THESE OPTIONS?| Talking dataPROBLEM: THE WAITING LINE TO QUERY DATAThe queue means a user wait is extended by each user in front of themUSERSSECONDSCPU| Talking dataQUERY’S BUILDING BLOCKS: THE INSTRUCTION SETS| Talking dataCROWD SPEED: MACHINE LEARNING ARCHITECTUREBreak each query into partsStore each ‘query part' and learn Build new queries with matching parts to boost performanceQUERYEXECUTIONSPEED| Talking dataRE-USE REPEATING INSTRUCTION SETS ACROSS QUERIES#1HOW MANY UNITS DID WE SELL?New Query#2WHAT WERE THE MONTHLY SALES?Already calculated units sold#3WHO WERE THE TOP SALES REPS EACH MONTH?Already calculated units sold & Monthly breakdown of unitsSimilar but non-identical queries| Talking dataMACHINE LEARNING BIWith Machine Learning BI, analytics get faster even when queries are not identical.The more questions you throw at it - the more efficient it gets!More users = more queries = faster resultsNo matchMatch found| Talking dataIN-CHIP = POWER + MACHINE LEARNINGLeverage the unique in-chip cache memory to perform faster than in-memoryWithout the limitation of having to load the entire model into RAMIn-Chip recognizes the CPU specs and applies its unique code to organize the query data in the CPUWhen needed again, that piece of data exists in the CPU cache, which is much faster than RAMIn-Chip machine-learns to fetch the associated compressed result sets in advanceSub-query results pre-loaded into L1 cache as compressed dataDecompressed images of that same data can be moved to the larger, but slower, L2 and L3 caches Decompression operations (read from and write to cache) are extremely fast| Talking dataIN-CHIP TECHNOLOGYThe best engine beer can buyIn memory columnar execution modeCACHE aware query kernelCACHE awaredecompressionInstruction recycling & learning algorithmsLLVM based compiler with SIMD supportFull 64BIT supportColumnar storage| Talking dataDataset: 120M rows 28GB8 Analytical queries X 50 cycles•Aggregations•Grouping•Top Ranking•Large intermediate results BENCHMARK SETTINGS160140120100806040200Test 1: No concurrencyTes...